1. Technical Field
The present invention relates in general to apparatus and methods for efficiently overriding net values in a logic simulator machine. More particularly, the present invention provides apparatus and methods for overriding net values in a logic simulator machine by inserting a multiplexer into a model for each net whose value can then be overridden.
2. Description of Related Art
Logic circuits in computer systems and related products have become increasingly large and complex. As a result, the initial design and fabrication have become increasingly more lengthy and costly. Although many efforts are made to eliminate any errors, it is no longer feasible to test the design only after the circuit has been fabricated. Accordingly, in recent years there has been increasing effort in design verification using computer modeling of the logic circuits before the circuit is actually embodied in hardware. The errors being referred to here are those produced by the interaction of logic circuits which are assumed to be operating correctly as separate entities but which are producing poor or incorrect results when operating together.
Logic technologies such as very large scale integrated circuits provide significant improvements in cost, performance, and reliability. However, they have disadvantages in that their fault diagnosis is more difficult than previous technologies and their engineering rework cycles needed to correct faults in logic design are greatly lengthened. These disadvantages exact great economic penalties for design errors and omissions and place a great emphasis on the goal of completely verifying designs in advance of engineering models.
Simulation has become a central part of verification methodology for circuit design. Applications span a wide spectrum, from early specifications to explore different architectural possibilities to the final stages of manufacturing test generation and fault coverage evaluation. For a long time, computer programs for use on a general purpose computer have been known which simulate such logic circuits. In these systems, the software program is run on any suitable general purpose computer. A model of the logic design is created. Test software programs may then be developed and executed using the model to analyze the operation of the logic design. However, as the number of gates on a single chip have reached into the range of hundreds of thousands to millions, these purely software simulators have required excessive amounts of computer time.
One approach used to overcome the excessive resource problem for full system simulation has been to build a hardware model of the design, essentially by hand wiring circuit boards with discrete components. Once wired, the circuit very quickly can emulate the desired circuit. A hardware emulator is a device which physically takes the place of the device to be emulated. A logic simulator machine, described below, could also act as a hardware emulator when the logic simulator machine is executing a model of the design if the appropriate wiring is attached to the logic simulator machine which will permit it to be physically coupled to other devices. However, a hardware model itself is costly and time consuming to build.
Another approach, which has found widespread acceptance, is a specialized logic simulator machine. These logic simulator machines as also sometimes called hardware accelerators. There are numerous logic simulation machines in existence for simulation, with different capacity, performance, and applications. These logic simulation machines range from small systems to significantly larger machines for simulating millions of gates. The term “logic simulator machine” as used herein will mean a hardware-based machine, and not a software-based simulation engine as described above.
One such logic simulator machine is described by U.S. Pat. No. 4,306,286 issued Dec. 15, 1981 to Cocke et al. This patent is herein incorporated by reference. The purpose of the logic simulator machine is to detect design errors in a simulated logic and enable the logic designer to correct the errors before the manufacture of the design.
The logic simulator machine described by Cocke et al. comprises a plurality of parallel basic processors which are interconnected through an inter-processor switch. The inter-processor switch provides communication not only among the basic processors which are the computing engine of the logic simulator machine, each simulating the individual gates of a portion of a logic model in parallel, but also between them and a control processor which provides overall control and input/output facilities of the logic simulator machine through a host computer to which the control processor is attached. Each basic processor contains the current state information for only the set of gates that is being simulated by that processor. When a basic processor simulates a gate whose input includes a connection to the output of a gate being simulated by a different processor, the state information for the gate is transferred over the inter-processor switch.
A representation of a logic design is first created in which Boolean gates, such as AND or OR gates, are used. A model of this representation is then built which may then be executed by the logic simulator machine. Test routines to test the design then may be executed using the model of the design which is being executed by the logic simulator machine.
A logical representation of a model which may be executed by a logic simulator machine is illustrated in FIG. 1 in accordance with the prior art. The numbers near the gates are the locations in instruction memory included in the logic simulator machine of the instructions representing the gates. They are also the locations in the current and next signal memory in the logic simulator machine holding the simulated gate outputs. These locations are also typically referred to as “nets”. Inputs are assumed to come from locations 5 and 6.
The logical representation of FIG. 1 includes a NAND gate 10 which receives a net 5 and a net 6 as its inputs. NAND 10 outputs a net 1 which is propagated to both NAND 12 and NAND 14 as an input. NAND 12 also receives net 5 as an input. NAND 14 also receives net 6 as an input. NAND 12 outputs net 2 as its output which is propagated to NAND 16 as an input. NAND 14 outputs net 3 as its output which is propagated to NAND 16 as an input. NAND 16 outputs net 4.
In order to test the circuit of FIG. 1 using a logic simulator machine, a model of the circuit is built. A test routine then may be executed using the model being executed by the logic simulator machine.
It may be useful when testing a circuit design to override a particular net while the test routine is being executed. One method in the prior art to override a net value was to replace the original function with an override function in the function memory. The override function will cause the override value to always be output for the net. For example, in the prior art, to override the current value of net 3, the original NAND function is replaced with an override function which will always output the override value for net 3. In the model for the circuit of FIG. 1, each NAND function is stored in function memory in the logic simulator machine. Each NAND function may be represented by a large number of bits. For example, in some systems, it may take from between 16 to 64 bits to represent a function. In order to override one NAND function, the model is modified by storing an override value in the function memory in place of the NAND function. The test routine is then executed using this modified model of the circuit. When the net is no longer to be overridden, the original function must then be stored back in function memory. In this example, the NAND function must be stored back in its appropriate function memory.
This process is repeated for each net value to be overridden. Often, many nets will need to be overridden for one or more cycles of execution of the test routine. It becomes very time consuming to store an override value, execute the test routine, and then restore the original function for each net, particularly when hundreds of nets may be overridden.
Therefore, a need exists for a method and system for efficiently overriding net values in a logic simulator machine.